The present invention relates to semiconductor devices, and particularly to forming source/drain regions and connections on fin field effect transistors.
Field effect transistors (FETs) are commonly employed in electronic circuit applications. FETs may include a source region and a drain region spaced apart by a semiconductor channel region. A gate, potentially including a gate dielectric layer, a work function metal layer, and a metal electrode, may be formed above the channel region. By applying voltage to the gate, the conductivity of the channel region may increase and allow current to flow from the source region to the drain region.
Fin field effect transistors (FinFETs) are an emerging technology which may provide solutions to field effect transistor (FET) scaling problems at, and below, the 22 nm node. FinFET structures may include at least a narrow semiconductor fin gated on at least two sides of each of the semiconductor fin, as well as a source region and a drain region adjacent to the fin on opposite sides of the gate. FinFET structures having n-type source and drain regions may be referred to as nFinFETs, and FinFET structures having p-type source and drain regions may be referred to as pFinFETs.
In some FinFET structures, different materials may be used for the fins of pFinFETs and nFinFETs in order to improve device performance. However, a material that may improve pFinFET performance may reduce nFET performance, and vice versa. For example, while pFinFET performance may be improved by forming fins made of silicon-germanium, nFinFET performance may instead be improved by forming fins made of undoped or carbon-doped silicon and may be degraded by forming fins made of silicon-germanium. Further, pFinFETs and nFinFETs are often fabricated on the same substrate.